Roadmap

Generics are a bounded slice (single type parameter, scalar, monomorphized). Closures, first-class functions and traits remain roadmap.

Core v1 conformance is defined and tested; see Conformance and Stability. Tagged-union enums with single- and multi-field i64 and f64 payloads construct, match and run, byte-identically across x86 and Arm CPU substrates on the deterministic integer path.

Both tiers are complete: control flow and constants (Tier 1), and algebraic data types with enum and struct (Tier 2). MIND expresses evidence-chained decisions alongside tensor computation; see the policy.mind design reference.

Its main governance consumer is MIND-Law (formerly 512-MIND), STARGA's implementation of the 512 constraint by Dr. J.M. Watson: nine invariants (I1–I9) that implement the seven canonical 512 conditions, plus six MIND-Law extensions (E1–E6) that are MIND-Law's own and not part of 512.

match takes EnumVariant, Literal, Ident and Wildcard patterns with block bodies. &expr and &mut expr are positionally disambiguated from bitwise & with no backtracking. The REAP attribute drives a dead-expert DCE pass, and non-MoE compiles see zero overhead. tensor<sparse[csr|csc|coo|bsr], dtype> is the type surface; CSR is the only concrete storage layout in v1.

Module-level gating only, no statement-level cfg. The CI bench gate was re-baselined against this surface and all suites stayed within the +2% gate.

default: full tensor stdlib, Q16.16 and heap (1.8 to 15.5 µs frontend). systems: stripped tensor, Q16.16, governance and heap (0.8 to 3 µs). embedded: stripped tensor, no heap, Q16.16 and governance (0.4 to 1 µs). The bench gate has per-profile criterion suites.

Still on the 0.3.0 track: the MIC binary header profile field and cross-profile linker refusal, so a systems cdylib cannot be linked into a default binary. Spec in mind-spec v1.0.

• Shipped: Phase 10 surface: shape types, operators, and the #[deterministic], #[target] and #[q16] annotations, held within the +7% bench-gate cap with the front end byte-identical
• Shipped: Phase 11 Tier 1 (v0.10.0): dense literals (9f807bd), in-function elementwise add, sub, mul and div, and tensor-returning functions via MLIR one-shot bufferization (cb43c90)
• Planned: Tier 2: deterministic intrinsics (zeros, ones, matmul, softmax, transpose, randn) and matmul vectorization for tensors; dense i64 matmul compiles today on the scalar mind-blas path
• Planned: Tier 3: inter-function tensor-argument calls; also sparse tensors and tensor-op fusion (Phase D)

Determinism tiers: int and Q16 are byte-identical cross-substrate (gated); scalar f64 and f32 are run-to-run bit-identical on the strict path, verified on x86_64 (AVX2) and ARM64 (NEON) hardware; vector and SIMD-reduction f32 is reproducible within a substrate except for the scoped fixtures the gate pins (cross-substrate work deferred to Phase 13.6). Spec: RFC 0012.

Each type gets a Q16.16 form and a strict f64 form, a pinned multiplication order, known-answer vectors, division that fails closed on zero divisors, and cross-substrate fixtures on AVX2 and NEON. Gates: keystone 7/7, cross-substrate identity on the new fixtures, value-oracle vectors, and every exported function running under mindc run. Operator overloading for these types (writing a * b) needs its own RFC and is not a prerequisite. No implementation yet.

Open question: whether it is worth a tier before a consumer asks. No RFC milestone or code yet.

std/vec.mind (8-byte stride, doubling growth), std/string.mind (Vec<u8>-shaped with a documented UTF-8 invariant), std/map.mind (parallel keys and vals arrays), std/io.mind (POSIX-shaped __mind_read and __mind_write). Every operation bottoms out in the i64 ABI; no built-in pointer type, no hidden allocator. The use std.foo resolver matches per-arg signatures against the imported declaration. MIND_STDLIB_PATH lets regulated deployments fork the stdlib without rebuilding mindc.

Five tags: v0.4.0 (Phase 2 and the Phase A use-import resolver), v0.4.1 (per-arg signature matching, return-type fidelity), v0.4.2 (stdlib bundled into the binary), v0.4.3 (MIND_STDLIB_PATH), v0.4.4 (named-struct parameter names in arity and type errors).

The bench gate was re-baselined at small_matmul 2.80 µs, medium_mlp 6.55 µs and large_network 17.10 µs, with the threshold loosened from +5% to +7% for hosted-runner variance. The work sits behind the std-surface and cross-module-imports flags, the default-build front end stayed byte-identical, and 65+ gated tests run in cloud CI. Honest scope: bounded first-version collections. The map is insert-only, allocation is region-based, and slices remain stubbed; a full general-purpose Vec, String and HashMap surface is roadmap.

• Shipped: Track A: six AVX2-accelerated __mind_blas_* intrinsics with scalar fallbacks, Q16.16 byte-identical scalar against SIMD at every input length
• Shipped: Track B: the compiler emits the MLIR vector dialect itself. v0.6.3 vector dot_f32 (fused 8-lane loop, no C shim), v0.6.4 Q16.16 vector dot and f32 L1/L∞, v0.6.5 Q16.16 vector L1, v0.6.6 vectorised row-major matmul within 1e-4 of an f64 oracle, v0.6.7 vector-load alignment fix
• Planned: Proposed 2026-10-03, not started: a kernel ablation harness (compute-only and pack/load-only variants), inference-shaped decode and prefill GEMM shapes, and a split-K guardrail that fixes the partial-sum combine order
• Planned: Deferred: @target per-call annotation, std.blas inlining

Pinned in the public cross-substrate gate on AVX2 and NEON: dot-l1-q16, dot-l2-q16, dot-i16-4096, gemv-q16, gemv-i16, gemm-q16 (plain and fused), gemm-i8 (single-thread, multi-thread and VNNI), and the scoped strict-float dot-f32-v-4093 and matmul-f32-v-64x64. CUDA sits on the commercial track and a photonic-projected Q16.16 path is research. Spec: RFC 0006.

All six phases landed in v0.6.8: the Mind.toml manifest types; mindc fmt with --check, --diff, --stdin and --fix; lint rule infrastructure with glob overrides; five named rules (q16_overflow, unused_import, naming_convention, shadowing, trailing_whitespace); the VCS-aware project driver; and the --fix pipeline with CI integration. Lint can be isolated with --no-fmt --no-typecheck. MINDCRAFT-001: pub is preserved through AST and formatter.

mindc fmt output is byte-identical for a fixed source and version, and idempotent; the lint stream is byte-identical for a fixed source, rule set and config. Measured within the +7% bench cap: vec.mind formats in 46 µs, mindc_mind/main.mind in 1.8 ms, and a full 117-file repo check runs in 23 ms. With this, the language, the compiler and the toolchain all self-host; few languages publicly reach all three rungs. Workflow: .github/workflows/mindcraft.yml.

• Shipped: A: single-crate build (--target, --emit, --release, --out). B: mindc test with #[test] and a parallel runner
• Shipped: C: workspaces with cross-crate topological sort and cycle detection. D: path dependencies with content-hash drift detection. E: git dependencies with a two-file Mind.lock scheme, enforced
• Shipped: F: incremental cache keyed on SHA-256 of source, flags and dep hashes; warm rebuild 3 ms against 188 ms cold (63x)
• Shipped: G (keystone): mindc build output byte-identical to direct invocation

The Rust crate still hosts mindc itself and remains the cargo install mind distribution path until RFC 0010 lands a pure-MIND libMLIR FFI. Spec: docs/rfcs/0008-mindc-build.md.

• Shipped: Phase A as std/async.mind, the 12th gated stdlib module: synchronous execution, cooperative cancellation, and a byte-stable FNV-1a trace_hash from the ReplayScheduler
• Planned: Phases B to F: a real executor (SingleThread and WorkStealing), async I/O (epoll, kqueue, IOCP), channels and structured supervision

Deterministic trace replay is the foundation for auditable governance pipelines. Spec: RFC 0011.

• Shipped: Tier 1: std.cli, std.io ANSI/TTY, std.string, std.tui, std.sha256
• In progress: Tier 2: pure-MIND crypto and TLS primitives verified against RFC and NIST known answers (AES-128-GCM, SHA-256, HKDF, X25519, X.509 parse and verify, Keccak/SHA-3 and SHAKE, RSA-PSS, ECDSA-P256, ML-KEM-768, and the TLS 1.3 key schedule, record layer and handshake crypto replayed against the RFC 8448 trace). A verified primitive library, not yet a connectable TLS client
• In progress: Tier 3: std.http HTTP/1.1 client phase 1 over plain TCP, HPACK (decode only) and HTTP/2 framing; HTTPS, chunked transfer and std.http.sse remain open
• Planned: Tier 4: async I/O (RFC 0011 Phases B to D). Tier 5: std.mcp client and server. Tier 6: the mindcraft-agent demo

Correctness first, not speed-optimized; the socket-driven TLS state machine and certificate-chain validation are the longest remaining pole. Spec: RFC 0013.

The CUDA backend runs on NVIDIA hardware: a caching device allocator that reuses buffers to avoid per-op cudaMalloc on the hot path, TF32 Tensor Cores via cuBLASLt with FP16 and FP8 for Ada Lovelace and newer, and float4-vectorized elementwise kernels targeting near-peak memory bandwidth. Benchmarked on an Ada-class GPU (sm_89); performance scales with the GPU.

GPU bit-identity is not part of the public CI gate. See Enterprise for licensing.

Targets NVIDIA Blackwell-class hardware (RTX Spark, GB10 and GB300 superchips), the forthcoming Vera Rubin generation, and AMD RDNA and CDNA (MI300, MI350, RDNA4), each as its own per-architecture target in the commercial mind-runtime. Today bit-identity and the evidence chain are verified on x86 and Arm CPUs only (integer, Q16.16 and scoped strict-float fixtures); hardware validation is gated on device availability.

The specification covers SLSA provenance attestations signed with the RFC 0016 post-quantum profile, SBOM generation (SPDX 3.0 and CycloneDX 1.5), OSV vulnerability scanning and policy enforcement gates. A public package registry with curated models is planned.

The outer boundary of the wedge is topological-quantum hardware (Microsoft Majorana 2): MIND can target gate scheduling there, but bit-identical determinism is physically impossible because a quantum measurement is probabilistic by nature.

IR tier mapping reserved: control flow on Si CMOS, tensor and conv on CNFET, weight residency and analog matmul on RRAM CIM. The analog to digital evidence boundary re-hashes RRAM-tier results so governance attests the digital wrapper without trusting the analog substrate, with per-device drift calibration and per-tier sparing hooks against the cited 0.01% per-CNT-layer defect ceiling.