Roadmap

v1.0 spec implemented. Static shapes, dtypes, compile-time shape verification, and full type system.

Core v1 conformance is defined and tested; see Conformance and Stability.

The foundational language specification with type system and core syntax.

Reverse-mode AD for all Core v1 ops: Add, Sub, Mul, Div, MatMul, Dot, Transpose, Sum, Mean, Reshape, Relu, Conv2d, and indexing/slicing operations.

Full gradient support for Core v1 operations including Conv2d.

MIND frontend processes programs in 1.8-15.5 µs (parse + typecheck + IR). 35,000-176,000x faster than PyTorch 2.10 GPU torch.compile(); 21,200-95,100x faster than JAX 0.9 cold-start XLA; 135,000-458,000x faster than Mojo 0.26.1. 100% bit-level determinism verified.

See Performance and Running Benchmarks for full details.

Python bindings, determinism verification, PyTorch comparison, and documentation complete.

Deterministic CPU backend via the MIND runtime interface (Phase-1 ops).

Production-ready CPU execution with optimized compilation.

GPU backend with CUDA acceleration, CachingAllocator (180x faster than PyTorch memory allocation), TF32 Tensor Cores via cuBLASLt, and float4 vectorized elementwise ops achieving 98% peak bandwidth. ROCm (AMD), Metal (Apple Silicon), WebGPU and WebNN backends shipped Apr 2026.

Production-ready across NVIDIA, AMD, and Apple GPUs plus WebGPU/WebNN. See Enterprise for details.

Full multi-vendor GPU acceleration with CUDA, ROCm, Metal, WebGPU, and WebNN backends. Memory optimization and Tensor Core support.

Full coverage of every accelerator class powering modern AI: CPU ✅, GPU ✅, TPU ✅, NPU ✅, LPU ✅, DPU ✅, FPGA ✅, ASIC ✅, Cerebras ✅, Taalas ✅, Tenstorrent ✅, SambaNova ✅, Graphcore IPU ✅, Intel Gaudi ✅.

TPU — Google systolic arrays via XLA HLO lowering (TPU v5e / v5p). NPU — on-device: Apple ANE, Qualcomm Hexagon, Intel NPU. LPU — Groq TSP, deterministic SRAM-resident streaming. DPU — NVIDIA BlueField-3 / AMD Pensando, 400 Gb/s wire-speed governance. FPGA — Xilinx Versal / Intel Agilex via HLS dataflow. ASIC — mind.asic.* dialect, XRM-SSD reference target. Cerebras — Wafer-Scale Engine WSE-2 / WSE-3, fabric-resident weights + streamed weights. Taalas — model-baked silicon with tape-out provenance cards. Tenstorrent — Wormhole / Blackhole Tensix mesh. SambaNova — RDU dataflow across PCU/PMU strips. Graphcore — Bow / Mk2 IPU with BSP supersteps. Gaudi — Intel Gaudi 2 / 3 with MME + TPC kernels.

Unified backend abstraction shipped: mindc --target {cpu | gpu | tpu | npu | lpu | dpu | fpga | asic | cerebras | taalas | tenstorrent | sambanova | ipu | gaudi}. Every backend is a deterministic MLIR lowering pass, governance-integrated, and tested in mind-runtime.

Full package manager with PubGrub CDCL resolver, content-addressed SHA-256 storage, sparse registry protocol, workspace support, and multi-version isolation (9.5K LOC).

Includes SLSA provenance attestations (Ed25519), SBOM generation (SPDX 3.0 + CycloneDX 1.5), OSV vulnerability scanning, and policy enforcement gates.

Production-ready package management with dependency resolution, security audit, and supply chain verification.

Governance logic runtime with enum and struct types, if/else and while control flow, const declarations, u32 bitfields, and bitwise operators. Byte-level operations via Rust FFI.

MIND is now a verifiable behavior language — expressing certified decisions alongside tensor computation. See policy.mind design reference.

Full two-tier implementation complete: control flow and constants (Tier 1), algebraic data types with enum and struct (Tier 2). Byte slices via Rust FFI.

Turn mindc from an executable-only compiler into a library emitter. Pub fn -> C symbol export, [exports] section honored, --profile CLI flag (0.2.6). cdylib emit, AOT native codegen, [protection] action transforms (0.3.0).

Foundation for Phase-2 native inference paths in mind-nerve, MindLLM, and rfn-mind. 1.8–15.5 µs frontend baseline preserved via module-level gating only.

Library-emit foundation in 0.2.6 (~2 weeks), cross-arch cdylib era in 0.3.0 (~6 weeks). Each item ships a dedicated sub-benchmark; CI gate enforces ±2% per size / ±1% mean against the headline numbers.

Three compile-target profiles selected via --profile=<default|systems|embedded>. default: full tensor stdlib + Q16.16 + heap (1.8-15.5 us frontend). systems: stripped tensor + Q16.16 + governance + heap (0.8-3 us). embedded: stripped tensor + no heap + Q16.16 + governance (0.4-1 us).

Same source code, three artifacts. Cross-profile linker refusal lands in 0.3.0 so a systems cdylib cannot be linked into a default binary. Spec in mind-spec v1.0.

Profile selection wired through codegen (0.2.6), MIC binary header profile field + cross-profile linker refusal (0.3.0). Bench gate has per-profile criterion suites.

Ultra-low latency runtime with streaming tensor executor, circular buffer ring allocator, fixed-point Q16.16 arithmetic, sub-millisecond latency profiling, DMA-safe memory pinning, and safety-critical mode with NaN/overflow/bounds checking.

<1ms inference latency verified. Pre-allocated memory pools and deterministic timing guarantees for medical device certification (ISO 62304, ISO 26262).

Full BCI runtime stack: streaming executor (Phase 13.1), safety-critical mode (Phase 13.3), and signal processing primitives for neuroscience applications.

Production-ready distributed training: TCP transport with connection pooling and ring topology, NCCL/Gloo backends, bandwidth-optimal RingAllReduce, pipeline parallelism with micro-batching, and comprehensive fault tolerance.

Elastic training with heartbeat monitoring, checkpoint recovery, and ClusterHealth tracking. See Distributed Execution Guide.

Full-stack distributed training with data/model/pipeline parallelism and elastic scaling.

Production-ready model serving: native + ONNX export with quantization, HTTP/gRPC inference server, dynamic batching, Prometheus metrics, Kubernetes health checks.

See Deployment Guide for deployment options and best practices.

Full model serving infrastructure with export, inference, metrics, and health monitoring.

Spec aligned with implementations. 20 IR instructions, 47 E-codes, 1e-5 numerical tolerance. 175+ compiler tests, 136 runtime tests, all passing.

Compiler and runtime implementations fully match spec. Conformance test suite complete.

All spec files aligned: ir.md, autodiff.md, ffi.md, runtime.md, types.md, errors.md. CHANGELOG.md present in all repos.

Specification-grade documentation across compiler, runtime, and spec repos.

5 MLIR dialects (arith, tensor, linalg, func, scf). Tested with LLVM 18. 7 FFI functions, 3 enums, 2 opaque types.

Full compiler workflow with CPU and GPU backends across CUDA, Metal, ROCm, WebGPU, and WebNN.