Backend Targets

Byte-identical by construction. MIND's wedge is a deterministic compiler whose integer-GEMM output is byte-identical across substrates by design, verified in CI today between x86 (AVX2) and Arm (NEON), with a tamper-evident evidence chain (a SHA-256 trace hash over the artifact's own IR) embedded in the artifact itself.

That guarantee rests on one decision: the deterministic path pins an exact-integer reduction.

1. int8 inputs
2. Exact int32 accumulateNo saturation, no fast-math
3. Fixed reduction order
4. Same output encoding

A target must preserve the admitted widths, range and overflow behavior, operation order, and output encoding. This is the contract we aim to extend to GPUs, RISC-V, and FPGA targets through conformance tests. The x86 ↔ Arm pair is verified in CI today. Each target has its own provenance; identical computational results do not imply identical signed artifacts or native binaries.

This page lists candidate chip families and their hardware status. A shipping chip or named runtime adapter is not a MIND conformance certificate. Only the admitted workloads on the verified CPU pair carry the output-identity evidence described above.

Status legend

Support matrix at a glance

Hardware status of each family, as described in the sections below. A status here describes the silicon and our lowering plan; it is not a conformance result.

x86: Intel and AMD

The reference substrate. Every modern x86 server and client core exposes an integer dot-product (VPDPBUSD-class, AVX-512 VNNI / AVX-VNNI-INT8) and the larger parts add a tile/matrix engine (Intel AMX), all with exact int32 accumulation and a fixed, architecturally-specified reduction order.

• Intel: Xeon Sapphire Rapids, Emerald Rapids, and Granite Rapids (VNNI + AMX-INT8) are Shipping and byte-identical. The E-core server and client lines (Sierra Forest, Clearwater Forest, Arrow/Lunar/Panther Lake) reach the same guarantee through the 256-bit VNNI-INT8 path: they simply select a different kernel, which the compiler handles by detecting CPU features, never by guessing from the fab process node. Next-gen Diamond Rapids (server) and Nova Lake (client), built on AVX10.2, are Announced; their integer path inherits the same exact-accumulate guarantee.
• AMD: EPYC and Ryzen on Zen 4 / Zen 5 (AVX-512 VNNI) are Shipping and byte-identical; Zen 6 (adding a dedicated int8 dot) is Announced. AMD's first x86 matrix engine, the jointly-standardized ACE tile extension on Zen 7, is Planned, and notably its published specification guarantees that the same integer result is always produced regardless of how an implementation tiles the work, which is exactly the property the wedge needs.

Arm and Apple

The cleanest “yes” of any vendor. Every Arm integer matrix/dot instruction (NEON/SVE2 SDOT/SMMLA and SME2 SMOPA outer-product-accumulate) multiplies int8 into exact int32 with two's-complement wrapping and no saturation, so the result is independent of vector length and internal reduction order.

• Arm Neoverse servers (V2/V3/N3: AWS Graviton, NVIDIA Grace, Microsoft Cobalt, Google Axion-class) are Shipping and byte-identical via the I8MM matrix path.
• Apple: the M4 generation's SME engine (SMOPA int8 → int32) is Shipping and byte-identical; it's the natural top rung of the Arm ladder. The newer M5 GPU neural accelerator (int8 → exact int32, programmable via Apple's Metal tensor APIs) is a Researching target: exact-integer accumulation is confirmed, but byte-identity to the CPU reference must be validated on-device.
• Arm client SME2 (Lumex C1) is Shipping; a future server core with SME2 is Planned (none is announced yet).
• Qualcomm Oryon CPUs (Snapdragon X / 8 Elite) are Shipping and byte-identical via the standard NEON int8 path.

GPU: NVIDIA and AMD

GPU integer tensor cores accumulate int8 into exact int32. The split-K / atomic nondeterminism that famously plagues floating-point GPU GEMM does not apply to integers: integer reduction is order-independent. So byte-identity is feasible on every shipping integer-tensor GPU, conditional on MIND owning the kernel (emitting the integer path directly and keeping the output as raw int32, rather than routing through a library's float dequant or low-precision fast path).

• NVIDIA: integer tensor cores (IMMA via mma.sync; warpgroup and tcgen05 paths on the newest parts) on Ampere, Ada, Hopper, and Blackwell are Shipping targets; Rubin is Announced. Note: the industry's pivot to 4-bit/8-bit floating-point (FP8/NVFP4/MXFP) formats is explicitly not part of the exact-integer wedge: those are floating-point and non-reproducible across substrates by design.
• AMD: CDNA MI300/MI350 (MFMA int8 → int32) and RDNA Radeon (WMMA, including native int4) are Shipping targets. RDNA additionally supports a packed-dot path whose reduction order is fully software-controlled: the cleanest way to byte-match the CPU reference on an AMD GPU.

Multi-vendor GPU execution (CUDA, ROCm, Metal, WebGPU, WebNN) ships in the commercial mind-runtime; deterministic native GPU codegen is a Researching capability in the commercial runtime.

RISC-V

The ratified, shippable path is the RVV 1.0 vector extension (widening int8 → int32 multiply-accumulate + widening reduction). This is the strongest determinism story of any non-CPU-tile substrate: the vector spec mandates a deterministic reduction structure, and for integers every valid reduction tree returns the identical wrapping result. RVV-1.0 cores (SiFive, Ventana, SpacemiT, Andes, T-Head and all RVA23 parts) are Shipping byte-identical targets.

• The faster int8 dot extension (Zvqdotq) and the RISC-V matrix extensions (IME / VME / AME) are Announced / Researching: drafts, not yet ratified, so we track them but do not pin codegen to unfrozen instruction encodings.
• Vendor matrix engines that ship ahead of the standard (SpacemiT, SiFive, Ventana, Tenstorrent) are Researching targets: exact-integer accumulate is feasible, but their internal tile-reduction order isn't publicly pinned yet, and any block-float intermediate path must be excluded from the byte-identical contract.

Cloud ASIC: TPU and Trainium

Systolic-array accelerators are structurally the most pinnable substrate: the dataflow physically fixes the reduction order, and integer accumulate is exact. The catch is access: these run through closed vendor compilers, so byte-identity to the CPU reference is conditional on pinning the compiler's tiling.

• Google TPU: v5e / v5p / v6e (Trillium) expose a native INT8 matrix path and are Planned byte-identical targets. Honest note: the newest v7 (Ironwood) pivots its matrix unit to FP8 floating-point; where a part drops native INT8 in favor of float, it falls outside the exact-integer wedge.
• AWS: Inferentia2 and Trainium1 carry a native INT8 systolic path (Planned). Trainium2/3 moved their matrix engines to FP8/MXFP floating-point: outside the integer wedge by the same principle.

We list these honestly: the wedge follows native integer matrix units, and we flag every family where the vendor has moved to floating-point.

Deterministic accelerators: Groq and FPGA

This is where the wedge is strongest: substrates whose reduction order is fixed by construction.

• FPGA (AMD/Xilinx Versal & UltraScale+ DSP58, Intel/Altera Agilex, Microchip PolarFire, Lattice, Achronix) is the gold-standard target and a Researching / Planned lowering path. A fixed bitstream physically pins the systolic/adder-tree reduction order: there is no runtime scheduler, no autotuning, no warp nondeterminism. The hardware is the pinned reduction order, with exact wide-integer accumulators (DSP58 int8 dot-product mode is a direct map). In pure-integer mode, byte-identity holds by construction.
• Groq LPU: the most on-thesis commercial chip in the landscape. Its architecture is statically scheduled with no caches, arbiters, or reorder buffers, and the vendor explicitly guarantees identical numerical results run-to-run and chip-to-chip. We treat Groq as a Researching target and the right candidate for a determinism collaboration: the determinism guarantee is real; matching it to MIND's exact-integer reference reduction order is the work.
• IBM NorthPole and digital in-memory-compute parts (e.g. d-Matrix, which deliberately chose digital over analog precisely to stay reproducible) are Researching targets on the same basis: digital, statically-scheduled, exact-integer.

Edge / NPU

On-device NPUs (Apple ANE, Qualcomm Hexagon, MediaTek APU, Google Edge TPU, and the Ryzen AI / Versal AI Engine family) almost all perform exact int8 → int32 MACs in hardware, so the arithmetic is reproducible. The practical blocker is access: most are closed runtimes with no hook to pin the reduction order or bypass vendor quantization.

• The AMD XDNA / Versal AI Engine family is the strongest edge candidate: its tiles use wide integer accumulators under a statically-scheduled dataflow with no runtime atomics, making it a Researching byte-identical target when MIND owns the compile-time schedule.
• The remaining mobile NPUs are Researching / access-gated: integer-exact in principle, but byte-identity to the CPU reference is not achievable today without vendor cooperation. Apple's ANE specifically dequantizes int8 to float before compute, which places it outside the exact-integer wedge.

Measurement and physical-noise boundaries

Physical observations require an explicit boundary around deterministic classical computation. The following devices may expose classical interfaces, but an output hash alone does not prove that independent noisy or probabilistic observations will match:

MIND's quantum roadmap aims to support hybrid classical/quantum programs through typed quantum operations, OpenQASM/QIR interoperability, simulator controls, and device conformance checks. A quantum execution backend has not shipped. This goal preserves exact classical output guarantees while giving measurement outcomes their own statistical contract; post-quantum signing is a separate capability.